chop.passes.transform.verilog

emit_verilog_top_transform_pass

chop.passes.graph.transforms.verilog.emit_verilog_top_transform_pass(graph, pass_args={})[source]

Emit the top-level model design in Verilog

Parameters:
  • graph (MaseGraph) – a MaseGraph

  • pass_args (_type_, optional) – this pass requires additional arguments which is explained below, defaults to {}

Returns:

return a tuple of a MaseGraph and an empty dict (no additional info to return)

Return type:

tuple(MaseGraph, Dict)

  • pass_args
    • project_dir -> str : the directory of the project for cosimulation

    • top_name -> str : top-level name

emit_verilog_tb_transform_pass

chop.passes.graph.transforms.verilog.emit_cocotb_transform_pass(graph, pass_args={})[source]

Emit test bench and related files for simulation

Parameters:
  • graph (MaseGraph) – a MaseGraph

  • pass_args (_type_, optional) – this pass requires additional arguments which is explained below, defaults to {}

Returns:

return a tuple of a MaseGraph and an empty dict (no additional info to return)

Return type:

tuple(MaseGraph, Dict)

  • pass_args
    • project_dir -> str : the directory of the project

    • trace -> bool : trace waves in the simulation

emit_bram_transform_pass

chop.passes.graph.transforms.verilog.emit_bram_transform_pass(graph, pass_args={})[source]

Enumerate input parameters of the node and emit a ROM block with handshake interface for each parameter

Parameters:
  • graph (MaseGraph) – a MaseGraph

  • pass_args (_type_, optional) – this pass requires additional arguments which is explained below, defaults to {}

Returns:

return a tuple of a MaseGraph and an empty dict (no additional info to return)

Return type:

tuple(MaseGraph, Dict)

  • pass_args
    • project_dir -> str : the directory of the project for cosimulation

    • top_name -> str : name of the top module

emit_mlir_hls_transform_pass

chop.passes.graph.transforms.verilog.emit_mlir_hls_transform_pass(graph, pass_args={})[source]

Emit the Verilog code of each module in the top-level model

emit_internal_rtl_transform_pass

chop.passes.graph.transforms.verilog.emit_internal_rtl_transform_pass(graph, pass_args={})[source]

Emit internal components