Lab 4 (Hardware Stream) Emitting Hardware

ELEC70109/EE9-AML3-10/EE9-AO25
Written by Aaron Zhao , Cheng Zhang , Pedro Gimenes

General introduction

In this lab, you will learn how to use MASE to emit hardware modules in SystemVerilog, and test the emitted hardware through Cocotb.

Most of the guidance are in lab4-hardware.ipynb, make sure you followed it closely and try to finish the following tasks and answer the questions.

Tasks

1. Read this page for more information on the hardware metadata pass. Why we have such a metadata setup? How is this different from the software metadata?

2. Read through top/hardware/rtl/top.sv and make sure you understand how our MLP model maps to this hardware design. Explain what each part is doing in the .sv file.

3. Launch the simulation, log and show the simulation results.

Extension Task

Choose another layer type from the Pytorch list and write a SystemVerilog file to implement that layer in hardware. Then, change the generated top.sv file to inject that layer within the design. For example, you may replace the ReLU activations with Leaky ReLU. Re-build the simulation and observe the effect on latency and accuracy.